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Andrea Pallotta

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2000
2EEAndrea Pallotta, Francesco Centurelli, Alessandro Trifiletti: A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. ISLPED 2000: 67-72
1998
1 Andrea Pallotta, Francesco Centurelli, Francesco Loriga, Alessandro Trifiletti: A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. SYBEN 1998: 183-190

Coauthor Index

1Francesco Centurelli [1] [2]
2Francesco Loriga [1]
3Alessandro Trifiletti [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)