| 2005 |
|---|
| 7 | EE | Viktor Fischer,
Milos Drutarovský,
Pawel Chodowiec,
F. Gramain:
InvMixColumn decomposition and multilevel resource sharing in AES implementations.
IEEE Trans. VLSI Syst. 13(8): 989-992 (2005) |
| 2003 |
|---|
| 6 | EE | Pawel Chodowiec,
Kris Gaj:
Very Compact FPGA Implementation of the AES Algorithm.
CHES 2003: 319-333 |
| 5 | EE | Peter Bellows,
Jaroslav Flidr,
Ladan Gharai,
Colin Perkins,
Pawel Chodowiec,
Kris Gaj:
IPsec-Protected Transport of HDTV over IP.
FPL 2003: 869-879 |
| 2001 |
|---|
| 4 | EE | Kris Gaj,
Pawel Chodowiec:
Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays.
CT-RSA 2001: 84-99 |
| 3 | EE | Pawel Chodowiec,
Po Khuon,
Kris Gaj:
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining.
FPGA 2001: 94-102 |
| 2 | EE | Pawel Chodowiec,
Kris Gaj,
Peter Bellows,
Brian Schott:
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board.
ISC 2001: 220-234 |
| 2000 |
|---|
| 1 | | Kris Gaj,
Pawel Chodowiec:
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.
AES Candidate Conference 2000: 40-54 |
