Pawel Chodowiec

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7EEViktor Fischer, Milos Drutarovský, Pawel Chodowiec, F. Gramain: InvMixColumn decomposition and multilevel resource sharing in AES implementations. IEEE Trans. VLSI Syst. 13(8): 989-992 (2005)
6EEPawel Chodowiec, Kris Gaj: Very Compact FPGA Implementation of the AES Algorithm. CHES 2003: 319-333
5EEPeter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj: IPsec-Protected Transport of HDTV over IP. FPL 2003: 869-879
4EEKris Gaj, Pawel Chodowiec: Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays. CT-RSA 2001: 84-99
3EEPawel Chodowiec, Po Khuon, Kris Gaj: Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. FPGA 2001: 94-102
2EEPawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott: Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. ISC 2001: 220-234
1 Kris Gaj, Pawel Chodowiec: Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. AES Candidate Conference 2000: 40-54

Coauthor Index

1Peter Bellows [2] [5]
2Milos Drutarovský [7]
3Viktor Fischer [7]
4Jaroslav Flidr [5]
5Kris Gaj [1] [2] [3] [4] [5] [6]
6Ladan Gharai [5]
7F. Gramain [7]
8Po Khuon [3]
9Colin Perkins [5]
10Brian Schott [2]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)