Hyuk-Jun Sung
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1999
1
EE
Hyuk-Jun Sung,
Kwang Sub Yoon
: A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.
ISCAS (2) 1999
: 553-556
Coauthor
Index
1
Kwang Sub Yoon
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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