2008 |
12 | EE | Ching-Yuan Yang,
Ken-Hao Chang:
Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications.
IEICE Transactions 91-A(1): 409-412 (2008) |
11 | EE | Ching-Yuan Yang,
Chih-Hsiang Chang,
Wen-Ger Wong:
A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology.
IEICE Transactions 91-A(2): 497-503 (2008) |
2007 |
10 | EE | Ching-Yuan Yang,
Jung-Mao Lin:
A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation.
IEICE Transactions 90-C(1): 196-200 (2007) |
2006 |
9 | EE | Hsin-Ming Wu,
Ching-Yuan Yang:
A 3.125-GHz Limiting Amplifier for Optical Receiver System.
APCCAS 2006: 210-213 |
8 | EE | Chia-Chieh Tu,
Ching-Yuan Yang:
A 6.5-GHz LC VCO with Integrated-Transformer Tuning.
APCCAS 2006: 510-513 |
7 | EE | Jun-Hong Weng,
Meng-Ting Tsai,
Jung-Mao Lin,
Ching-Yuan Yang:
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique.
ISCAS 2006 |
6 | EE | Meng-Ting Tsai,
Ching-Yuan Yang:
A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels.
ISCAS 2006 |
5 | EE | Jun-Hong Weng,
Chong-Jng Yu,
Ching-Yuan Yang,
Peng-Chang Yang:
A low-noise microsensor amplifier with automatic gain control system.
ISCAS 2006 |
4 | EE | Ching-Yuan Yang,
Meng-Ting Tsai:
High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique.
IEICE Transactions 89-C(11): 1567-1574 (2006) |
3 | EE | Ching-Yuan Yang,
Yu Lee,
Cheng-Hsing Lee:
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector.
IEICE Transactions 89-C(6): 746-752 (2006) |
2005 |
2 | EE | Ching-Yuan Yang,
Yu Lee:
A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques.
ISCAS (2) 2005: 1150-1153 |
1 | EE | Ching-Yuan Yang,
Jen-Wen Chen,
Meng-Ting Tsai:
A high-frequency phase-compensation fractional-N frequency synthesizer.
ISCAS (5) 2005: 5091-5094 |