| |
| 2006 | ||
|---|---|---|
| 2 | EE | Ching-Yuan Yang, Yu Lee, Cheng-Hsing Lee: A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector. IEICE Transactions 89-C(6): 746-752 (2006) |
| 2005 | ||
| 1 | EE | Ching-Yuan Yang, Yu Lee: A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. ISCAS (2) 2005: 1150-1153 |
| 1 | Cheng-Hsing Lee | [2] |
| 2 | Ching-Yuan Yang | [1] [2] |