| 2007 |
|---|
| 6 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Physical aware clock skew rescheduling.
ACM Great Lakes Symposium on VLSI 2007: 473-476 |
| 5 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Effective Acceleration of Iterative Slack Distribution Process.
ISCAS 2007: 1077-1080 |
| 2006 |
|---|
| 4 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Clock Skew Scheduling Under Process Variations.
ISQED 2006: 237-242 |
| 3 | EE | Xinjie Wei,
Yici Cai,
Meng Zhao,
Xianlong Hong:
Legitimate Skew Clock Routing with Buffer Insertion.
VLSI Signal Processing 42(2): 107-116 (2006) |
| 2005 |
|---|
| 2 | EE | Xinjie Wei,
Yici Cai,
Xianlong Hong:
Zero skew clock routing with tree topology construction using simulated annealing method.
ISCAS (1) 2005: 101-104 |
| 2004 |
|---|
| 1 | | Meng Zhao,
Xinjie Wei,
Yici Cai,
Xianlong Hong:
Quick and effective buffered legitimate skew clock routing.
ISCAS (5) 2004: 337-340 |
