Yeong-Luh Ueng

List of publications from the DBLP Bibliography Server - FAQ

2008

5 EE Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang: VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. ISCAS 2008: 520-523

4 EE Yeong-Luh Ueng, Yen-Ming Chen: A Turbo Coded MIMO Scheme for Noncoherent Fast-Fading Channels. VTC Spring 2008: 1350-1354

2007

3 EE Yung-Chih Tsai, Yeong-Luh Ueng: A Tail-Biting Turbo Coded OFDM System for PAPR and BER Reduction. VTC Fall 2007: 1067-1071

2 EE Yeong-Luh Ueng, Chung-Chao Cheng: A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards. VTC Fall 2007: 1255-1259

1 EE Yeong-Luh Ueng, Yu-Lung Wu, Ruey-Yi Wei: Concatenated space-time block coding with trellis coded modulation using a delay processor. IEEE Transactions on Wireless Communications 6(12): 4452-4463 (2007)

2008
5	EE	Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang: VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. ISCAS 2008: 520-523
4	EE	Yeong-Luh Ueng, Yen-Ming Chen: A Turbo Coded MIMO Scheme for Noncoherent Fast-Fading Channels. VTC Spring 2008: 1350-1354
2007
3	EE	Yung-Chih Tsai, Yeong-Luh Ueng: A Tail-Biting Turbo Coded OFDM System for PAPR and BER Reduction. VTC Fall 2007: 1067-1071
2	EE	Yeong-Luh Ueng, Chung-Chao Cheng: A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards. VTC Fall 2007: 1255-1259
1	EE	Yeong-Luh Ueng, Yu-Lung Wu, Ruey-Yi Wei: Concatenated space-time block coding with trellis coded modulation using a delay processor. IEEE Transactions on Wireless Communications 6(12): 4452-4463 (2007)

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