| |
| 2008 | ||
|---|---|---|
| 1 | EE | Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang: VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. ISCAS 2008: 520-523 |
| 1 | Yeong-Luh Ueng | [1] |
| 2 | Yu-Lun Wang | [1] |
| 3 | Zong-Cheng Wu | [1] |
| 4 | Chung-Jay Yang | [1] |