| 2007 |
|---|
| 5 | EE | Tingyuan Nie,
Masahiko Toyonaga:
An Efficient and Reliable Watermarking System for IP Protection.
IEICE Transactions 90-A(9): 1932-1939 (2007) |
| 2005 |
|---|
| 4 | EE | Tingyuan Nie,
Tomoo Kisaka,
Masahiko Toyonaga:
A watermarking system for IP protection by a post layout incremental router.
DAC 2005: 218-221 |
| 3 | EE | Tingyuan Nie,
Tomoo Kisaka,
Masahiko Toyonaga:
A post layout watermarking method for IP protection.
ISCAS (6) 2005: 6206-6209 |
| 2000 |
|---|
| 2 | EE | Masahiko Toyonaga,
Keiichi Kurokawa,
Takuya Yasui,
Atsushi Takahashi:
A practical clock tree synthesis for semi-synchronous circuits.
ISPD 2000: 159-164 |
| 1994 |
|---|
| 1 | | Masahiko Toyonaga,
Shih-Tsung Yang,
Toshiro Akino,
Isao Shirakawa:
A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout.
ISCAS 1994: 185-188 |
