1995 | ||
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3 | EE | Shang-E Tai, Debashis Bhattacharya: A three-stage partial scan design method to ease ATPG. J. Electronic Testing 7(1-2): 95-104 (1995) |
1994 | ||
2 | Shang-E Tai, Debashis Bhattacharya: A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. VLSI Design 1994: 101-106 | |
1993 | ||
1 | Shang-E Tai, Debashis Bhattacharya: Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. ICCD 1993: 564-567 |
1 | Debashis Bhattacharya | [1] [2] [3] |