Michael A. Riepe

2003
5	EE	Michael A. Riepe, Karem A. Sakallah: Transistor placement for noncomplementary digital VLSI cell synthesis. ACM Trans. Design Autom. Electr. Syst. 8(1): 81-107 (2003)
1999
4	EE	Michael A. Riepe, Karem A. Sakallah: Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. ISPD 1999: 74-81
1998
3	EE	Michael A. Riepe, Karem A. Sakallah: The edge-based design rule model revisited. ACM Trans. Design Autom. Electr. Syst. 3(3): 463-486 (1998)
1996
2	EE	Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown: Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Trans. VLSI Syst. 4(1): 113-129 (1996)
1993
1		Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown: Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. ICCD 1993: 361-364

Coauthor Index

1	Richard B. Brown	[1] [2]
2	Karem A. Sakallah	[1] [2] [3] [4] [5]
3	João P. Marques Silva (João Marques-Silva)	[1] [2]