T. K. Priya

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2006

4 EE T. K. Priya, K. Sridharan: A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. Microprocessors and Microsystems 30(1): 1-14 (2006)

3 EE T. K. Priya, P. Rajesh Kumar, K. Sridharan: A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. Microprocessors and Microsystems 30(7): 413-424 (2006)

2004

2 EE T. K. Priya, K. Sridharan: An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. VLSI Design 2004: 1057-1062

1 EE K. Sridharan, T. K. Priya: A parallel algorithm for constructing reduced visibility graph and its FPGA implementation. Journal of Systems Architecture 50(10): 635-644 (2004)

2006
4	EE	T. K. Priya, K. Sridharan: A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. Microprocessors and Microsystems 30(1): 1-14 (2006)
3	EE	T. K. Priya, P. Rajesh Kumar, K. Sridharan: A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. Microprocessors and Microsystems 30(7): 413-424 (2006)
2004
2	EE	T. K. Priya, K. Sridharan: An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. VLSI Design 2004: 1057-1062
1	EE	K. Sridharan, T. K. Priya: A parallel algorithm for constructing reduced visibility graph and its FPGA implementation. Journal of Systems Architecture 50(10): 635-644 (2004)

Coauthor Index

1 P. Rajesh Kumar [3]

2 K. Sridharan [1] [2] [3] [4]