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Ravindranath Naiknaware

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1999
6EERavindranath Naiknaware, Terri S. Fiez: Switched-capacitor integrator design optimizing for power and process variations. ISCAS (2) 1999: 278-281
5EERavindranath Naiknaware, Terri S. Fiez: Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. ISCAS (2) 1999: 33-36
1998
4EERavindranath Naiknaware, Terri S. Fiez: CMOS analog circuit stack generation with matching constraints. ICCAD 1998: 371-375
1993
3 Ravindranath Naiknaware: Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. ICCD 1993: 318-321
2 Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa: Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. ITC 1993: 139-148
1 Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin: Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. VLSI Design 1993: 140-143

Coauthor Index

1Rajeev Arora [1]
2Terri S. Fiez [4] [5] [6]
3Srinivasa Rao Kasa [2]
4John Larkin [1]
5G. N. Nandakumar [1] [2]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)