1999 |
6 | EE | Ravindranath Naiknaware,
Terri S. Fiez:
Switched-capacitor integrator design optimizing for power and process variations.
ISCAS (2) 1999: 278-281 |
5 | EE | Ravindranath Naiknaware,
Terri S. Fiez:
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer.
ISCAS (2) 1999: 33-36 |
1998 |
4 | EE | Ravindranath Naiknaware,
Terri S. Fiez:
CMOS analog circuit stack generation with matching constraints.
ICCAD 1998: 371-375 |
1993 |
3 | | Ravindranath Naiknaware:
Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment.
ICCD 1993: 318-321 |
2 | | Ravindranath Naiknaware,
G. N. Nandakumar,
Srinivasa Rao Kasa:
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation.
ITC 1993: 139-148 |
1 | | Ravindranath Naiknaware,
G. N. Nandakumar,
Rajeev Arora,
John Larkin:
Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach.
VLSI Design 1993: 140-143 |