| 2008 |
|---|
| 5 | EE | Silvio Misera,
Heinrich Theodor Vierhaus,
André Sieber:
Simulated fault injections and their acceleration in SystemC.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 270-278 (2008) |
| 2007 |
|---|
| 4 | EE | Heinrich Theodor Vierhaus,
Helmut Rossmann,
Silvio Misera:
Timing- / Power-Optimization for Digital Logic Based on Standard Cells.
DSD 2007: 303-306 |
| 3 | EE | Silvio Misera,
Heinrich Theodor Vierhaus,
André Sieber:
Fault Injection Techniques and their Accelerated Simulation in SystemC.
DSD 2007: 587-595 |
| 2006 |
|---|
| 2 | EE | Silvio Misera,
Heinrich Theodor Vierhaus,
Lars Breitenfeld,
André Sieber:
A Mixed Language Fault Simulation of VHDL and SystemC.
DSD 2006: 275-279 |
| 2004 |
|---|
| 1 | EE | Silvio Misera,
Heinrich Theodor Vierhaus:
FIT - A Parallel Hierarchical Fault Simulation Environment.
PARELEC 2004: 289-294 |
