| |
| 2008 | ||
|---|---|---|
| 4 | EE | Andrzej Pulka, Adam Milik: VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. FDL 2008: 118-123 |
| 2007 | ||
| 3 | EE | Adam Milik, Andrzej Pulka: Common HDL-Matlab Simulation Environment. FDL 2007: 68-73 |
| 2006 | ||
| 2 | EE | Andrzej Pulka: SystemC models generation based on libraries of templates. ISCAS 2006 |
| 1999 | ||
| 1 | EE | Jerzy Dabrowski, Andrzej Pulka: Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique. DATE 1999: 790-791 |
| 1 | Jerzy Dabrowski | [1] |
| 2 | Adam Milik | [3] [4] |