| 2003 |
|---|
| 7 | EE | Hajime Shimada,
Hideki Ando,
Toshio Shimada:
Pipeline stage unification: a low-energy consumption technique for future mobile processors.
ISLPED 2003: 326-329 |
| 2002 |
|---|
| 6 | EE | Ryo Fujioka,
Kiyokazu Katayama,
Ryotaro Kobayashi,
Hideki Ando,
Toshio Shimada:
A preactivating mechanism for a VT-CMOS cache using address prediction.
ISLPED 2002: 247-250 |
| 1999 |
|---|
| 5 | EE | Ryotaro Kobayashi,
Yukihiro Ogawa,
Hideki Ando,
Toshio Shimada,
Mitsuaki Iwata:
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.
EUROMICRO 1999: 1432-1440 |
| 1998 |
|---|
| 4 | EE | Chikako Nakanishi,
Hideki Ando,
Tetsuya Hara,
Masao Nakaya:
Software pipelining with path selection.
Systems and Computers in Japan 29(9): 74-86 (1998) |
| 1996 |
|---|
| 3 | EE | Tetsuya Hara,
Hideki Ando,
Chikako Nakanishi,
Masao Nakaya:
Performance Comparison of ILP Machines with Cycle Time Evaluation.
ISCA 1996: 213-224 |
| 1995 |
|---|
| 2 | EE | Hideki Ando,
Chikako Nakanishi,
Tetsuya Hara,
Masao Nakaya:
Unconstrained Speculative Execution with Predicated State Buffering.
ISCA 1995: 126-137 |
| 1993 |
|---|
| 1 | | Hideki Ando,
Chikako Nakanishi,
Hirohisa Machida,
Tetsuya Hara,
Satoru Kishida,
Masao Nakaya:
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.
ICCD 1993: 106-113 |
