| 2008 |
|---|
| 21 | EE | Norihiro Takahashi,
Kazuhide Fujita,
Tadashi Shibata:
An analog self-similitude edge-filtering processor for multiple-resolution image perception.
ISCAS 2008: 1640-1643 |
| 20 | EE | Hitoshi Hayakawa,
Tadashi Shibata:
Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception.
ISCAS 2008: 3526-3529 |
| 2006 |
|---|
| 19 | EE | Benjamas Tongprasit,
Tadashi Shibata:
Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI.
ISCAS 2006 |
| 2005 |
|---|
| 18 | EE | Benjamas Tongprasit,
Kiyoto Ito,
Tadashi Shibata:
A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering.
ISCAS (3) 2005: 2389-2392 |
| 17 | EE | Tomoyuki Nakayama,
Toshihiko Yamasaki,
Tadashi Shibata:
A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter.
ISCAS (6) 2005: 5365-5368 |
| 16 | EE | Yusuke Nakashita,
Yoshio Mita,
Tadashi Shibata:
An Analog Visual Pre-Processing Processor.
NIPS 2005 |
| 2004 |
|---|
| 15 | EE | Tomoyuki Nakayama,
Toshihiko Yamasaki,
Tadashi Shibata:
Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters.
ISCAS (1) 2004: 425-428 |
| 14 | EE | Masayuki Umejima,
Toshihiko Yamasaki,
Tadashi Shibata:
A bump-circuit-based motion detector using projected-activity histograms.
ISCAS (1) 2004: 749-752 |
| 13 | | Hideo Yamasaki,
Tadashi Shibata:
A real-time VLSI median filter employing two-dimensional bit-propagating architecture.
ISCAS (2) 2004: 349-352 |
| 2003 |
|---|
| 12 | EE | Masakazu Yagi,
Hideo Yamasaki,
Tadashi Shibata:
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors.
NIPS 2003 |
| 11 | EE | Masakazu Yagi,
Tadashi Shibata,
Chihiro Tanikawa,
Kenji Takada:
A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation.
SCIA 2003: 534-540 |
| 2002 |
|---|
| 10 | EE | Keng Hoong Wee,
T. Yonezawa,
Toshiyuki Nozawa,
Tadashi Shibata,
Tadahiro Ohmi:
A zone-programmed EEPROM with real-time write monitoring for analog data storage.
ISCAS (4) 2002: 655-658 |
| 9 | EE | Huaiyu Xu,
Yoshio Mita,
Tadashi Shibata:
Intelligent Internet Search Applications Based on VLSI Associative Processors.
SAINT 2002: 230-237 |
| 2001 |
|---|
| 8 | EE | Keng Hoong Wee,
Toshiyuki Nozawa,
T. Yonezawa,
Y. Yamashita,
Tadashi Shibata,
Tadahiro Ohmi:
High-precision analog EEPROM with real-time write monitoring.
ISCAS (1) 2001: 105-108 |
| 7 | EE | Toshihiko Yamasaki,
Tadashi Shibata:
Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology.
NIPS 2001: 1131-1138 |
| 1999 |
|---|
| 6 | EE | Tadahiro Ohmi,
Tadashi Shibata,
Koji Kotani,
Tsutomu Nakai,
Akira Nakada,
Ning Mei Yu,
Masahiro Konda,
Tatsuo Morimoto,
Yuichiro Yamashita:
Association hardware for intelligent electronic systems.
Systems and Computers in Japan 30(12): 52-62 (1999) |
| 1998 |
|---|
| 5 | EE | Tadashi Shibata:
Functional-Device-Based VLSI for Intelligent Electronic Systems.
ISMVL 1998: 317- |
| 4 | EE | Tadashi Shibata:
Right brain computing hardware: a psychological brain model on silicon.
KES (3) 1998: 429-435 |
| 3 | EE | Tatsuo Morimoto,
Tadashi Shibata,
Tadahiro Ohmi:
Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing.
KES (3) 1998: 436-441 |
| 1995 |
|---|
| 2 | EE | Tadashi Shibata,
Tsutomu Nakai,
Tatsuo Morimoto,
Ryu Kaihara,
Takeo Yamashita,
Tadahiro Ohmi:
Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing.
NIPS 1995: 685-691 |
| 1993 |
|---|
| 1 | EE | Tadashi Shibata,
Koji Kotani,
Takeo Yamashita,
Hiroshi Ishii,
Hideo Kosaka,
Tadahiro Ohmi:
Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors.
NIPS 1993: 919-926 |
