| 2004 |
|---|
| 5 | EE | Deepak D. Sherlekar:
Design considerations for regular fabrics.
ISPD 2004: 97-102 |
| 1996 |
|---|
| 4 | EE | John Y. Sayah,
Rajesh Gupta,
Deepak D. Sherlekar,
Philip S. Honsinger,
Jitendra M. Apte,
S. Wayne Bollinger,
Hai Hsia Chen,
Sumit DasGupta,
Edward P. Hsieh,
Andrew D. Huber,
Edward J. Hughes,
Zahi M. Kurzum,
Vasant B. Rao,
Thepthai Tabtieng,
Vigen Valijan,
David Y. Yang:
Design planning for high-performance ASICs.
IBM Journal of Research and Development 40(4): 431-452 (1996) |
| 1990 |
|---|
| 3 | | Deepak D. Sherlekar:
Optimality of Gauge and Degree-Sensitive VLSI Layouts of Planar Graphs.
ICCI 1990: 507-516 |
| 1988 |
|---|
| 2 | | Deepak D. Sherlekar,
Joseph JáJá:
Input Sensitive VLSI Layouts for Graphs of Arbitrary Degree.
AWOC 1988: 268-277 |
| 1985 |
|---|
| 1 | | Deepak D. Sherlekar,
Shaunak Pawagi,
I. V. Ramakrishnan:
O(1) Parallel Time Incremental Graph Algorithms.
FSTTCS 1985: 477-495 |
