| 2004 |
|---|
| 4 | | Masahiro Sakamoto,
Shuusaku Mizukami,
Daisuke Hamano,
Hisato Fujisaka:
A design of 4-operand redundant binary parallel adder using neuron MOS.
ISCAS (2) 2004: 793-796 |
| 3 | | Hisato Fujisaka,
Daisuke Hamano,
Masahiro Sakamoto,
Takeshi Kamio:
A binary-quantized pseudo-diffusion system.
ISCAS (4) 2004: 720-723 |
| 2002 |
|---|
| 2 | EE | Masahiro Sakamoto,
Daisuke Hamano,
Mititada Morisue:
Design of a multiple-operand redundant binary adder.
Systems and Computers in Japan 33(10): 1-9 (2002) |
| 1998 |
|---|
| 1 | EE | Mititada Morisue,
Jun Endo,
Toshimitu Morooka,
Nobuhiro Shimizu,
Masahiro Sakamoto:
A Josephson Ternary Memory Circuit.
ISMVL 1998: 19-24 |
