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| 1999 | ||
|---|---|---|
| 2 | EE | W. De Rammelaere, K. Eckert, T. Lawell, R. McGarity, F. Steininger, P. Le Moenner, E. Hilkens: Catalyst: A DSIP Design Flow Development in Industry. ISSS 1999: 122-127 |
| 1989 | ||
| 1 | EE | Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man: Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. DAC 1989: 513-518 |
| 1 | Ivo Bolsens | [1] |
| 2 | Luc J. M. Claesen | [1] |
| 3 | K. Eckert | [2] |
| 4 | E. Hilkens | [2] |
| 5 | T. Lawell | [2] |
| 6 | Hugo De Man | [1] |
| 7 | R. McGarity | [2] |
| 8 | P. Le Moenner | [2] |
| 9 | F. Steininger | [2] |