| |
| 2001 | ||
|---|---|---|
| 1 | T. Lundquist, E. Delenia, J. Harroun, E. LeRoy, C.-C. Tsao: Ultra-Thinning of C4 Integrated Circuits for Backside Analysis during First Silicon Debug. Microelectronics Reliability 41(9-10): 1545-1549 (2001) | |
| 1 | E. Delenia | [1] |
| 2 | J. Harroun | [1] |
| 3 | T. Lundquist | [1] |
| 4 | C.-C. Tsao | [1] |