| 2008 |
|---|
| 5 | EE | S. Ramakrishnan,
K. T. Lau:
Improved Dynamic Current Mode Logic for Low Power Applications.
Journal of Circuits, Systems, and Computers 17(2): 183-190 (2008) |
| 4 | EE | W. J. Yang,
Y. Zhou,
K. T. Lau:
Low Power Adiabatic Programmable Logic Array with Single Clock Iapdl.
Journal of Circuits, Systems, and Computers 17(2): 211-219 (2008) |
| 2002 |
|---|
| 3 | EE | H. H. Wong,
K. T. Lau:
Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family.
Journal of Circuits, Systems, and Computers 11(2): 155-164 (2002) |
| 2000 |
|---|
| 2 | EE | K. W. Ng,
K. T. Lau:
A Novel Adiabatic Register File Design.
Journal of Circuits, Systems, and Computers 10(1-2): 67-76 (2000) |
| 1999 |
|---|
| 1 | EE | K. W. Ng,
K. T. Lau:
An Adiabatic 4: 2 Compressor Design for Low Power VLSI.
Journal of Circuits, Systems, and Computers 9(5-6): 339-346 (1999) |
