S. Koeppe

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1987

2 EE S. Koeppe: Optimal Layout to Avoid CMOS Stuck-Open Faults. DAC 1987: 829-835

1986

1 S. Koeppe: Modeling and Simulation of Delay Faults in CMOS Logic Circuits. ITC 1986: 530-537

1987
2	EE	S. Koeppe: Optimal Layout to Avoid CMOS Stuck-Open Faults. DAC 1987: 829-835
1986
1		S. Koeppe: Modeling and Simulation of Delay Faults in CMOS Logic Circuits. ITC 1986: 530-537