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| 2007 | ||
|---|---|---|
| 3 | EE | M. Watanabe, F. Kobayashi: A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ASP-DAC 2007: 124-125 |
| 2006 | ||
| 2 | EE | M. Watanabe, F. Kobayashi: Optically Reconfigurable Gate Arrays vs. ASICs. APCCAS 2006: 1164-1167 |
| 1986 | ||
| 1 | K. Moriwaki, S. Ishiyama, K. Takizawa, F. Kobayashi, S. Sekine, Y. Hinataze: A Test System tor High Density and High Speed Digital Board. ITC 1986: 993-996 | |
| 1 | Y. Hinataze | [1] |
| 2 | S. Ishiyama | [1] |
| 3 | K. Moriwaki | [1] |
| 4 | S. Sekine | [1] |
| 5 | K. Takizawa | [1] |
| 6 | M. Watanabe | [2] [3] |