2008 |
18 | EE | Akira Utagawa,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution.
IEICE Transactions 91-A(9): 2475-2481 (2008) |
2007 |
17 | EE | Gessyca Maria Tovar,
Eric Shun Fukuda,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning.
ICONIP (2) 2007: 117-126 |
16 | EE | Gessyca Maria Tovar,
Eric Shun Fukuda,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning.
IJCNN 2007: 897-901 |
15 | EE | Ken Ueno,
Tetsuya Hirose,
Tetsuya Asai,
Yoshihito Amemiya:
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs.
ISCAS 2007: 3748-3751 |
14 | EE | Motoyoshi Takahashi,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors.
I. J. Bifurcation and Chaos 17(5): 1713-1719 (2007) |
13 | EE | Akira Utagawa,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits.
IEICE Transactions 90-A(10): 2108-2115 (2007) |
12 | EE | Kazuki Nakada,
Tetsuya Asai,
Tetsuya Hirose,
Hatsuo Hayashi,
Yoshihito Amemiya:
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters.
Neurocomputing 71(1-3): 3-12 (2007) |
2006 |
11 | EE | Tetsuya Asai,
Taishi Kamiya,
Tetsuya Hirose,
Yoshihito Amemiya:
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator.
I. J. Bifurcation and Chaos 16(1): 207-212 (2006) |
10 | EE | Ken Ueno,
Tetsuya Hirose,
Tetsuya Asai,
Yoshihito Amemiya:
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy.
IEICE Transactions 89-A(4): 902-907 (2006) |
2005 |
9 | EE | Sungwoo Cha,
Tetsuya Hirose,
Masaki Haruoka,
Toshimasa Matsuoka,
Kenji Taniguchi:
A CMOS IF Variable Gain Amplifier with Exponential Gain Control.
IEICE Transactions 88-A(2): 410-415 (2005) |
8 | EE | Tetsuya Hirose,
Toshimasa Matsuoka,
Kenji Taniguchi,
Tetsuya Asai,
Yoshihito Amemiya:
Ultralow-Power Current Reference Circuit with Low Temperature Dependence.
IEICE Transactions 88-C(6): 1142-1147 (2005) |
7 | EE | Tetsuya Asai,
Masayuki Ikebe,
Tetsuya Hirose,
Yoshihito Amemiya:
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata.
Parallel Algorithms Appl. 20(1): 57-67 (2005) |
2004 |
6 | EE | Yusuke Kanazawa,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
A MOS circuit for bursting neural oscillators with excitable oregonators.
IEICE Electronic Express 1(4): 73-76 (2004) |
5 | EE | Masayuki Furuhashi,
Tetsuya Hirose,
Hiroshi Tsuji,
Masayuki Tachi,
Kenji Taniguchi:
Atomic configuration of boron pile-up at the Si/SiO2 interface.
IEICE Electronic Express 1(6): 126-130 (2004) |
4 | EE | Hiroshi Matsubara,
Tetsuya Asai,
Tetsuya Hirose,
Yoshihito Amemiya:
Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata.
IEICE Electronic Express 1(9): 248-252 (2004) |
2000 |
3 | EE | Takeo Hosomi,
Yasushi Kanoh,
Masaaki Nakamura,
Tetsuya Hirose:
A DSM Architecture for a Parallel Computer Cenju-4.
HPCA 2000: 287- |
1999 |
2 | | Yasushi Kanoh,
Masaaki Nakamura,
Tetsuya Hirose,
Takeo Hosomi,
Hirokazu Takayama,
Toshiyuki Nakata:
Message Passing Communication in a Parallel Computer Cenju-4.
ISHPC 1999: 55-70 |
1993 |
1 | | Tsutomu Maruyama,
Tetsuya Hirose,
Akihiko Konagaya:
A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems.
ICGA 1993: 184-190 |