| 2008 |
|---|
| 3 | EE | Liangpeng Guo,
Yici Cai,
Qiang Zhou,
Le Kang,
Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network.
ACM Great Lakes Symposium on VLSI 2008: 255-260 |
| 2 | EE | Liangpeng Guo,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.
IEICE Transactions 91-A(8): 2084-2090 (2008) |
| 2007 |
|---|
| 1 | EE | Liangpeng Guo,
Yici Cai,
Qiang Zhou,
Xianlong Hong:
Logic and Layout Aware Voltage Island Generation for Low Power Design.
ASP-DAC 2007: 666-671 |
