Sri Raga Sudha Garimella

2008
2	EE	Sri Raga Sudha Garimella, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal: Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor. ISCAS 2008: 1492-1495
1	EE	Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín, Ramón González Carvajal: An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators. VLSI Design 2008: 294-299

Coauthor Index

1	Ramón González Carvajal	[1] [2]
2	Annajirao Garimella	[1]
3	Lalitha Mohana Kalyani-Garimella	[1]
4	Antonio J. López-Martín	[1] [2]
5	Jaime Ramírez-Angulo	[1] [2]