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| 2005 | ||
|---|---|---|
| 1 | EE | Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev: Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. DATE 2005: 126-131 |
| 1 | Fang Liu | [1] |
| 2 | Sule Ozev | [1] |
| 3 | Devaka V. Yasaratne | [1] |