Goran L. Djordjevic

List of publications from the DBLP Bibliography Server - FAQ

2004

5 EE Goran L. Djordjevic, Mile K. Stojcev, Tatjana R. Stankovic: Approach to partially self-checking combinational circuits design. Microelectronics Journal 35(12): 945-952 (2004)

4 EE Mile K. Stojcev, Goran L. Djordjevic, Tatjana R. Stankovic: Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits. Microelectronics Reliability 44(1): 173-178 (2004)

1996

3 Goran L. Djordjevic, Milorad B. Tosic: A Compile-Time Scheduling Heuristic for Multiprocessor Architectures. Comput. J. 39(8): 663-674 (1996)

2 Goran L. Djordjevic, Mile K. Stojcev: An Interprocessor Communication Interface for Message Passing via Shared Memory Modules - Design and Performance. Computers and Artificial Intelligence 15(1): (1996)

1 Goran L. Djordjevic, Milorad B. Tosic: A Heuristic for Scheduling Task Graphs with Communication Delays Onto Multiprocessors. Parallel Computing 22(9): 1197-1214 (1996)

2004
5	EE	Goran L. Djordjevic, Mile K. Stojcev, Tatjana R. Stankovic: Approach to partially self-checking combinational circuits design. Microelectronics Journal 35(12): 945-952 (2004)
4	EE	Mile K. Stojcev, Goran L. Djordjevic, Tatjana R. Stankovic: Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits. Microelectronics Reliability 44(1): 173-178 (2004)
1996
3		Goran L. Djordjevic, Milorad B. Tosic: A Compile-Time Scheduling Heuristic for Multiprocessor Architectures. Comput. J. 39(8): 663-674 (1996)
2		Goran L. Djordjevic, Mile K. Stojcev: An Interprocessor Communication Interface for Message Passing via Shared Memory Modules - Design and Performance. Computers and Artificial Intelligence 15(1): (1996)
1		Goran L. Djordjevic, Milorad B. Tosic: A Heuristic for Scheduling Task Graphs with Communication Delays Onto Multiprocessors. Parallel Computing 22(9): 1197-1214 (1996)

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