| |
| 2005 | ||
|---|---|---|
| 2 | EE | Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton: Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. ISVLSI 2005: 290-291 |
| 2003 | ||
| 1 | EE | Damian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O'Kane, Rob Quigley, Declan O'Connor: APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator. FPL 2003: 1162-1165 |
| 1 | Vivian Bessler | [1] |
| 2 | Damian Dalton | [1] [2] |
| 3 | Jeffrey Griffiths | [1] |
| 4 | Alexander Maili | [2] |
| 5 | Andrew McCarthy | [1] |
| 6 | Declan O'Connor | [1] |
| 7 | Rory O'Kane | [1] |
| 8 | Christian Steger | [2] |
| 9 | Abhay Vadher | [1] |
| 10 | Reinhold Weiss | [2] |