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Slo-Li Chu

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2007
12EESlo-Li Chu: Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture. EUC 2007: 234-246
11EESlo-Li Chu: Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. LCPC 2007: 261-275
2005
10EESlo-Li Chu: An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture. EUC 2005: 281-290
9EESlo-Li Chu: POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture. ICPADS (2) 2005: 699-703
2004
8EESlo-Li Chu: PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture. ICPADS 2004: 690-
7EESlo-Li Chu, Tsung-Chuan Huang: SAGE: an automatic analyzing system for a new high-performance SoC architecture--processor-in-memory. Journal of Systems Architecture 50(1): 1-15 (2004)
6EESlo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee: Improving workload balance and code optimization on processor-in-memory systems. Journal of Systems and Software 71(1-2): 71-82 (2004)
2003
5EETsung-Chuan Huang, Slo-Li Chu: A statement based parallelizing framework for processor-in-memory architectures. Inf. Process. Lett. 85(3): 159-163 (2003)
2001
4 Tsung-Chuan Huang, Slo-Li Chu: A new analyzing approach for intelligent memory systems. Computers and Their Applications 2001: 452-457
3 Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee: Improving Workload Balance and Code Optimization in Processor-in-Memory Systems. ICPADS 2001: 273-278
2 Tsung-Chuan Huang, Slo-Li Chu: A Comprehensive Statement-Based Analysis System for Tightly-Coupled Heterogeneous Environments. ISCA PDCS 2001: 248-253
2000
1EETsung-Chuan Huang, Slo-Li Chu: SAGE: A New Analysis and Optimization System for FlexRAM Architecture. Intelligent Memory Systems 2000: 160-168

Coauthor Index

1Tsung-Chuan Huang [1] [2] [3] [4] [5] [6] [7]
2Lan-Chi Lee [3] [6]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)