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Rachid Beguenane

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2006
4EERachid Beguenane, Jean-Gabriel Mailloux, Stéphane Simard, Arnaud Tisserand: Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time. CCECE 2006: 1073-1077
3EERachid Beguenane, Mohand A. Ouhrouche, Andrzej M. Trzynadlowski: A new scheme for sensorless induction motor control drives operating in low speed region. Mathematics and Computers in Simulation 71(2): 109-120 (2006)
2005
2EEStéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin: A 2005 review of FPGA arithmetic (abstract only). FPGA 2005: 276
2004
1 Luc Morin, Rachid Beguenane, Stéphane Simard, Éric Larouche: A new bit-serial multiplier architecture for area-efficient fpga implementation. Circuits, Signals, and Systems 2004: 333-338

Coauthor Index

1Éric Larouche [1] [2]
2Jean-Gabriel Mailloux [4]
3Luc Morin [1] [2]
4Mohand A. Ouhrouche [3]
5Stéphane Simard [1] [2] [4]
6Arnaud Tisserand [4]
7Andrzej M. Trzynadlowski [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)