Abhaya Asthana

2006
21	EE	Abhaya Asthana, Seon Kim: Multimedia Servers. Encyclopedia of Multimedia 2006
20	EE	Abhaya Asthana: Multimedia in Education. Encyclopedia of Multimedia 2006
19	EE	Abhaya Asthana, Eric J. Bauer, Meenakshi Sharma, Xuemei Zhang: End-to-end availability considerations for services over IMS. Bell Labs Technical Journal 11(3): 199-210 (2006)
18	EE	Bernard L. Malone III, Abhaya Asthana: Analyzing network availability of a mobile data network: A case study. Bell Labs Technical Journal 11(3): 47-56 (2006)
2000
17	EE	Harvey I. Epstein, Abhaya Asthana, Stephen A. Corum, Leen Mak: Hybrid network management. Bell Labs Technical Journal 5(4): 63-79 (2000)
1997
16	EE	Abhaya Asthana, James Sienicki, Mani B. Srivastava: Kaleido: An Environment for Composing Networked Multimedia Applications. HPDC 1997: 181-190
15	EE	Abhaya Asthana, Nandit Soparkar, H. V. Jagadish, Paul Krzyzanowski: Logic-enhanced memory for high performance databases. KES (2) 1997: 517-524
1995
14	EE	Nandit Soparkar, Paul Krzyzanowski, H. V. Jagadish, Abhaya Asthana: Run-Time Parallelization of Sequential Database Programs. CIKM 1995: 74-81
1994
13		Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski: An Experimental Active-Memory-Based Network Environment. HPDC 1994: 139-146
12		Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski: SWIM Active Memory: Architecture and Applications. IFIP Congress (1) 1994: 183-188
11		Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski: Towards a Programming Environment for a Computer with Intelligent Memory. IFIP PACT 1994: 89-98
10		Abhaya Asthana, Paul Krzyzanowski: A Memory Participative Architecture for High Performance Communication Systems. INFOCOM 1994: 167-174
9		Abhaya Asthana, Mike Laznovsky, Boyd Mathews: SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. VLSI Design 1994: 33-38
1991
8		Abhaya Asthana, H. V. Jagadish, Paul Krzyzanowski: The Design of a Back-end Object Management System. Code Generation 1991: 294-319
1989
7		Abhaya Asthana, H. V. Jagadish, Boyd Mathews: Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer. ICPP (1) 1989: 323-327
6		Abhaya Asthana, Cheryl J. Briggs, Mark R. Cravats, Boyd Mathews: The Architecture of Massively Parallel Numeric Processor. IFIP Congress 1989: 891-891
5		Abhaya Asthana, H. V. Jagadish, Scott C. Knauer: An Intelligent Memory Transaction Engine. IWDM 1989: 286-300
1988
4		Abhaya Asthana, Boyd Mathews, Cheryl J. Briggs, Mark R. Cravats: A VLSI Building Block for Massively Parallel Computation. FGCS 1988: 879-886
3	EE	J. A. Chandross, H. V. Jagadish, Abhaya Asthana: The trap as a control flow mechanism. MICRO 1988: 50-52
1982
2		Sudhir Ahuja, Abhaya Asthana: A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling. ASPLOS 1982: 205-209
1978
1		Abhaya Asthana: Design and Control of a Three-Stage Switch Matrix in the Presence of Fan-Out. IEEE Trans. Computers 27(10): 886-895 (1978)

Coauthor Index

1	Sudhir Ahuja	[2]
2	Eric J. Bauer	[19]
3	Cheryl J. Briggs	[4] [6]
4	J. A. Chandross	[3]
5	Stephen A. Corum	[17]
6	Mark R. Cravats	[4] [6]
7	Mark Cravatts	[11] [12] [13]
8	Harvey I. Epstein	[17]
9	H. V. Jagadish	[3] [5] [7] [8] [14] [15]
10	Seon Kim	[21]
11	Scott C. Knauer	[5]
12	Paul Krzyzanowski	[8] [10] [11] [12] [13] [14] [15]
13	Mike Laznovsky	[9]
14	Leen Mak	[17]
15	Bernard L. Malone III	[18]
16	Boyd Mathews	[4] [6] [7] [9]
17	Meenakshi Sharma	[19]
18	James Sienicki	[16]
19	Nandit Soparkar	[14] [15]
20	Mani B. Srivastava	[16]
21	Xuemei Zhang	[19]

Colors in the list of coauthors