Rong-Jyi Yang

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2005

2 EE Rong-Jyi Yang, Shen-Iuan Liu: A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. IEICE Transactions 88-C(6): 1248-1252 (2005)

1 EE Rong-Jyi Yang, Shen-Iuan Liu: A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. IEICE Transactions 88-C(8): 1726-1730 (2005)

2005
2	EE	Rong-Jyi Yang, Shen-Iuan Liu: A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. IEICE Transactions 88-C(6): 1248-1252 (2005)
1	EE	Rong-Jyi Yang, Shen-Iuan Liu: A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. IEICE Transactions 88-C(8): 1726-1730 (2005)

Coauthor Index

1 Shen-Iuan Liu [1] [2]