| 2007 |
|---|
| 10 | EE | Che-Fu Liang,
Sy-Chyuan Hwu,
Shen-Iuan Liu:
A Multi-Band Burst-Mode Clock and Data Recovery Circuit.
IEICE Transactions 90-C(4): 802-810 (2007) |
| 2006 |
|---|
| 9 | EE | Chi-Nan Chuang,
Shen-Iuan Liu:
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology.
IEICE Transactions 89-C(3): 295-299 (2006) |
| 8 | EE | Shao-Ku Kao,
Shen-Iuan Liu:
All-Digital Clock Deskew Buffer with Variable Duty Cycles.
IEICE Transactions 89-C(6): 753-760 (2006) |
| 2005 |
|---|
| 7 | EE | Hua-Chin Lee,
Chien-Chih Lin,
Chia-Hsin Wu,
Shen-Iuan Liu,
Chorng-Kuang Wang,
Hen-Wai Tsao:
A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications.
ISCAS (1) 2005: 368-371 |
| 6 | EE | Chien-Hung Kuo,
Chang-Hung Chen,
Huang-Shih Lin,
Shen-Iuan Liu:
A tunable bandpass /spl Delta//spl Sigma/ modulator using double sampling.
ISCAS (4) 2005: 3676-3679 |
| 5 | EE | Rong-Jyi Yang,
Shen-Iuan Liu:
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs.
IEICE Transactions 88-C(6): 1248-1252 (2005) |
| 4 | EE | Rong-Jyi Yang,
Shen-Iuan Liu:
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector.
IEICE Transactions 88-C(8): 1726-1730 (2005) |
| 2004 |
|---|
| 3 | EE | Chia-Hsin Wu,
Jieh-Wei Liao,
Shen-Iuan Liu:
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors.
ISCAS (1) 2004: 1044-1047 |
| 2002 |
|---|
| 2 | EE | Chih-Chun Tang,
Chia-Hsin Wu,
Kun-Hsien Li,
Tai-Cheng Lee,
Shen-Iuan Liu:
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network.
ISCAS (3) 2002: 77-80 |
| 2001 |
|---|
| 1 | EE | Lee-An Ho,
Shr-Lung Chen,
Chien-Hung Kuo,
Shen-Iuan Liu:
CMOS oversampling Sigma-Delta magnetic to digital converters.
ISCAS (1) 2001: 388-391 |
