| 2007 |
|---|
| 25 | EE | Satoshi Yamane:
Theory and Practice of Probabilistic Timed Game for Embedded Systems.
ICESS 2007: 109-120 |
| 2005 |
|---|
| 24 | EE | Satoshi Yamane:
Timed Weak Simulation Verification and Its Application to Stepwise Refinement of Real-Time Software.
EUC 2005: 381-394 |
| 23 | EE | Satoshi Yamane:
Automata-Theoretic Performance Analysis Method of Soft Real-Time Systems.
EUC Workshops 2005: 1211-1224 |
| 22 | EE | Satoshi Yamane:
Deductive Probabilistic Verification Methods of Safety, Liveness and Nonzenoness for Distributed Real-Time Systems.
ICESS 2005: 332-345 |
| 21 | EE | Yosuke Mutsuda,
Takaaki Kato,
Satoshi Yamane:
Specification and Verification Techniques of Embedded Systems Using Probabilistic Linear Hybrid Automata.
ICESS 2005: 346-360 |
| 20 | EE | Yosuke Mutsuda,
Takaaki Kato,
Satoshi Yamane:
Symbolic Reachability Analysis of Probabilistic Linear Hybrid Automata.
IEICE Transactions 88-A(11): 2972-2981 (2005) |
| 2004 |
|---|
| 19 | EE | Satoshi Yamane,
Takashi Kanatani:
Deductive Probabilistic Verification Methods for Embedded and Ubiquitous Computing.
EUC 2004: 183-195 |
| 18 | EE | Satoshi Yamane:
Deductive Verification of Probabilistic Real-Time Systems.
ICDCS Workshops 2004: 622-627 |
| 17 | EE | Satoshi Yamane,
Kazuhiro Nakamura:
Development and evaluation of symbolic model checker based on approximation for real-time systems.
Systems and Computers in Japan 35(10): 83-101 (2004) |
| 2003 |
|---|
| 16 | EE | Satoshi Yamane:
Probabilistic Timed Simulation Verification and Its Application to Stepwise Refinement of Real-Time Systems.
ASIAN 2003: 276-290 |
| 15 | EE | Satoshi Yamane:
Deductive Schedulability Verification Methodology of Real-Time Software using both Refinement Verification and Hybrid Automata.
COMPSAC 2003: 527-533 |
| 14 | EE | Satoshi Yamane:
Formal Probabilistic Refinement Verification of Embedded Real-Time Systems.
WSTFEUS 2003: 79-82 |
| 1999 |
|---|
| 13 | EE | Y. Tachi,
Satoshi Yamane:
Real-Time Symbolic Model Checking for Hard Real-Time Systems.
RTCSA 1999: 496- |
| 1998 |
|---|
| 12 | EE | Kazuhiro Nakamura,
Satoshi Yamane:
Formal Verification of Real-Time Software by Symbolic Model-Checker.
ACSD 1998: 99-108 |
| 11 | | Satoshi Yamane:
A Practical Hierarchical Design by Timed Simulation Relations for Real-Time Systems.
FM-Trends 1998: 151-167 |
| 10 | EE | Satoshi Yamane:
Hierarchical Design Method for Real-Time Distributed Systems.
RTCSA 1998: 189- |
| 9 | EE | Kazuhiko Eguchi,
Satoshi Yamane,
Hideo Sugi,
Kenji Oshima:
Sensing of Arc Length and Wire Extension Using Neural Network in Robotic Welding.
Rough Sets and Current Trends in Computing 1998: 163-170 |
| 8 | EE | Satoshi Yamane,
Kazuhiro Okada,
Kenji Shinoda,
Kenji Oshima:
Traffic Signal Control Using Multi-layered Fuzzy Control.
Rough Sets and Current Trends in Computing 1998: 171-177 |
| 7 | EE | Kazuhiko Eguchi,
Junya Suzuki,
Satoshi Yamane,
Kenji Oshima:
An Application of Genetic Algorithms to Floorplanning of VLSI.
Rough Sets and Current Trends in Computing 1998: 263-270 |
| 1997 |
|---|
| 6 | | Satoshi Yamane:
Formal Specification and Verification Method of Concurrent and Distributed Systems by Restricted Timed Automata.
ARTS 1997: 169-183 |
| 5 | | Satoshi Yamane,
Kazuhiro Nakamura:
Symbolic Model-Checking Method Based on Approximations and Binary Decision Diagrams for Real-Time Systems.
TACS 1997: 562-582 |
| 4 | EE | Satoshi Yamane:
A method for the specification and verification of distributed systems by a timed automaton.
Systems and Computers in Japan 28(2): 11-20 (1997) |
| 1995 |
|---|
| 3 | EE | Satoshi Yamane:
Formal Timing Verification Techniques for Distributed System .
FTDCS 1995: 454-460 |
| 2 | | Satoshi Yamane:
Real-Time Object-Oriented Method.
OOIS 1995: 287-302 |
| 1 | EE | Satoshi Yamane:
Verification system for real-time specification based on extended real-time logic.
RTCSA 1995: 192-196 |
