Satoshi Yamane

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25EESatoshi Yamane: Theory and Practice of Probabilistic Timed Game for Embedded Systems. ICESS 2007: 109-120
24EESatoshi Yamane: Timed Weak Simulation Verification and Its Application to Stepwise Refinement of Real-Time Software. EUC 2005: 381-394
23EESatoshi Yamane: Automata-Theoretic Performance Analysis Method of Soft Real-Time Systems. EUC Workshops 2005: 1211-1224
22EESatoshi Yamane: Deductive Probabilistic Verification Methods of Safety, Liveness and Nonzenoness for Distributed Real-Time Systems. ICESS 2005: 332-345
21EEYosuke Mutsuda, Takaaki Kato, Satoshi Yamane: Specification and Verification Techniques of Embedded Systems Using Probabilistic Linear Hybrid Automata. ICESS 2005: 346-360
20EEYosuke Mutsuda, Takaaki Kato, Satoshi Yamane: Symbolic Reachability Analysis of Probabilistic Linear Hybrid Automata. IEICE Transactions 88-A(11): 2972-2981 (2005)
19EESatoshi Yamane, Takashi Kanatani: Deductive Probabilistic Verification Methods for Embedded and Ubiquitous Computing. EUC 2004: 183-195
18EESatoshi Yamane: Deductive Verification of Probabilistic Real-Time Systems. ICDCS Workshops 2004: 622-627
17EESatoshi Yamane, Kazuhiro Nakamura: Development and evaluation of symbolic model checker based on approximation for real-time systems. Systems and Computers in Japan 35(10): 83-101 (2004)
16EESatoshi Yamane: Probabilistic Timed Simulation Verification and Its Application to Stepwise Refinement of Real-Time Systems. ASIAN 2003: 276-290
15EESatoshi Yamane: Deductive Schedulability Verification Methodology of Real-Time Software using both Refinement Verification and Hybrid Automata. COMPSAC 2003: 527-533
14EESatoshi Yamane: Formal Probabilistic Refinement Verification of Embedded Real-Time Systems. WSTFEUS 2003: 79-82
13EEY. Tachi, Satoshi Yamane: Real-Time Symbolic Model Checking for Hard Real-Time Systems. RTCSA 1999: 496-
12EEKazuhiro Nakamura, Satoshi Yamane: Formal Verification of Real-Time Software by Symbolic Model-Checker. ACSD 1998: 99-108
11 Satoshi Yamane: A Practical Hierarchical Design by Timed Simulation Relations for Real-Time Systems. FM-Trends 1998: 151-167
10EESatoshi Yamane: Hierarchical Design Method for Real-Time Distributed Systems. RTCSA 1998: 189-
9EEKazuhiko Eguchi, Satoshi Yamane, Hideo Sugi, Kenji Oshima: Sensing of Arc Length and Wire Extension Using Neural Network in Robotic Welding. Rough Sets and Current Trends in Computing 1998: 163-170
8EESatoshi Yamane, Kazuhiro Okada, Kenji Shinoda, Kenji Oshima: Traffic Signal Control Using Multi-layered Fuzzy Control. Rough Sets and Current Trends in Computing 1998: 171-177
7EEKazuhiko Eguchi, Junya Suzuki, Satoshi Yamane, Kenji Oshima: An Application of Genetic Algorithms to Floorplanning of VLSI. Rough Sets and Current Trends in Computing 1998: 263-270
6 Satoshi Yamane: Formal Specification and Verification Method of Concurrent and Distributed Systems by Restricted Timed Automata. ARTS 1997: 169-183
5 Satoshi Yamane, Kazuhiro Nakamura: Symbolic Model-Checking Method Based on Approximations and Binary Decision Diagrams for Real-Time Systems. TACS 1997: 562-582
4EESatoshi Yamane: A method for the specification and verification of distributed systems by a timed automaton. Systems and Computers in Japan 28(2): 11-20 (1997)
3EESatoshi Yamane: Formal Timing Verification Techniques for Distributed System . FTDCS 1995: 454-460
2 Satoshi Yamane: Real-Time Object-Oriented Method. OOIS 1995: 287-302
1EESatoshi Yamane: Verification system for real-time specification based on extended real-time logic. RTCSA 1995: 192-196

Coauthor Index

1Kazuhiko Eguchi [7] [9]
2Takashi Kanatani [19]
3Takaaki Kato [20] [21]
4Yosuke Mutsuda [20] [21]
5Kazuhiro Nakamura [5] [12] [17]
6Kazuhiro Okada [8]
7Kenji Oshima [7] [8] [9]
8Kenji Shinoda [8]
9Hideo Sugi [9]
10Junya Suzuki [7]
11Y. Tachi [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)