2007 | ||
---|---|---|
2 | EE | Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka: A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery. DSN 2007: 256-265 |
2006 | ||
1 | EE | Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura: Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. IEICE Transactions 89-C(6): 844-850 (2006) |
1 | Yuichi Abe | [1] |
2 | Kesami Hagiwara | [1] |
3 | Kazuya Hirayanagi | [1] |
4 | Teppei Hirotsu | [2] |
5 | Takeshi Kataoka | [1] [2] |
6 | Teruaki Sakata | [2] |
7 | Takanori Shimura | [1] |
8 | Yasuo Sugure | [1] |
9 | Seiji Takeuchi | [1] |
10 | Akihiko Tomita | [1] |