Jyun-Yi Wu
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2007
1
EE
Chi-Chang Lu
, Jyun-Yi Wu,
Tsung-Sum Lee
: A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.
ISCAS 2007
: 1955-1958
Coauthor
Index
1
Tsung-Sum Lee
[
1
]
2
Chi-Chang Lu
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
