| |
| 2007 | ||
|---|---|---|
| 4 | EE | Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee: A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. ISCAS 2007: 1955-1958 |
| 2005 | ||
| 3 | EE | Tsung-Sum Lee, Chi-Chang Lu, Shen-Hau Yu, Jian-Ting Zhan: A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal. ISCAS (4) 2005: 3111-3114 |
| 2003 | ||
| 2 | EE | Tsung-Sum Lee, Chi-Chang Lu: A fully differential low-voltage CMOS high-speed track-and-hold circuit. ISCAS (1) 2003: 397-400 |
| 2002 | ||
| 1 | EE | Tsung-Sum Lee, Chi-Chang Lu: A low-voltage fully differential CMOS high-speed track-and-hold circuit. APCCAS (1) 2002: 141-144 |
| 1 | Tsung-Sum Lee | [1] [2] [3] [4] |
| 2 | Jyun-Yi Wu | [4] |
| 3 | Shen-Hau Yu | [3] |
| 4 | Jian-Ting Zhan | [3] |