| |
| 2008 | ||
|---|---|---|
| 3 | EE | Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi: A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator. IEICE Transactions 91-B(5): 1397-1402 (2008) |
| 2007 | ||
| 2 | EE | Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi: A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution. IEICE Transactions 90-C(1): 165-170 (2007) |
| 2006 | ||
| 1 | EE | Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi: A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. ISCAS 2006 |
| 1 | Woo-Young Choi | [1] [2] [3] |
| 2 | Seung-Woo Lee | [1] [2] [3] |