| 2008 |
|---|
| 6 | EE | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator.
IEICE Transactions 91-B(5): 1397-1402 (2008) |
| 2007 |
|---|
| 5 | EE | Myung-Il Roh,
Kyu-Yeul Lee,
Woo-Young Choi:
Rapid generation of the piping model having the relationship with a hull structure in shipbuilding.
Advances in Engineering Software 38(4): 215-228 (2007) |
| 4 | EE | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution.
IEICE Transactions 90-C(1): 165-170 (2007) |
| 2006 |
|---|
| 3 | EE | Pyung-Su Han,
Woo-Young Choi:
1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS.
ISCAS 2006 |
| 2 | EE | Chang-Kyung Seong,
Seung-Woo Lee,
Woo-Young Choi:
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution.
ISCAS 2006 |
| 1 | EE | Ki-Hyuk Lee,
Jae-Wook Lee,
Woo-Young Choi:
A 0.18 µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link.
IEICE Transactions 89-C(10): 1454-1459 (2006) |
