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| 1999 | ||
|---|---|---|
| 1 | EE | Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi: A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design. ISPD 1999: 9-15 |
| 1 | Masato Iwabuchi | [1] |
| 2 | Takashi Omachi | [1] |
| 3 | Noboru Sakamoto | [1] |