| 2008 |
|---|
| 6 | EE | Yufeng Lu,
Erdal Oruklu,
Jafar Saniie:
Fpga-based hardware/software co-design for chirplet signal decomposition.
ACM Great Lakes Symposium on VLSI 2008: 347-350 |
| 5 | EE | Erdal Oruklu,
Vibhuti B. Dave,
Jafar Saniie:
Performance analysis of flagged prefix adders with logical effort.
ISCAS 2008: 684-687 |
| 2007 |
|---|
| 4 | EE | Nathan Jachimiec,
Fernando Martinez-Vallin,
Jafar Saniie:
CReconfigurable finite field instruction set architecture.
FPGA 2007: 216-220 |
| 3 | EE | Vibhuti B. Dave,
Erdal Oruklu,
Jafar Saniie:
Design and Synthesis of a Three Input Flagged Prefix Adder.
ISCAS 2007: 1081-1084 |
| 2 | EE | John Moskal,
Erdal Oruklu,
Jafar Saniie:
Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.
ISCAS 2007: 1089-1092 |
| 2004 |
|---|
| 1 | | Erdal Oruklu,
Jafar Saniie:
Multiplierless architectures for frequency-diverse target detection algorithms.
Circuits, Signals, and Systems 2004: 404-409 |
