| |
| 2008 | ||
|---|---|---|
| 6 | EE | Minoru Saeki, Daisuke Suzuki: Security Evaluations of MRSL and DRSL Considering Signal Delays. IEICE Transactions 91-A(1): 176-183 (2008) |
| 5 | EE | Daisuke Suzuki, Minoru Saeki: An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style. IEICE Transactions 91-A(1): 184-192 (2008) |
| 2007 | ||
| 4 | EE | Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Transactions 90-A(1): 160-168 (2007) |
| 3 | EE | Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa: Leakage Analysis of DPA Countermeasures at the Logic Level. IEICE Transactions 90-A(1): 169-178 (2007) |
| 2006 | ||
| 2 | EE | Daisuke Suzuki, Minoru Saeki: Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. CHES 2006: 255-269 |
| 2005 | ||
| 1 | EE | Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: DPA Leakage Models for CMOS Logic Circuits. CHES 2005: 366-382 |
| 1 | Tetsuya Ichikawa | [1] [3] [4] |
| 2 | Daisuke Suzuki | [1] [2] [3] [4] [5] [6] |