| 2007 |
|---|
| 5 | EE | Daisuke Suzuki,
Minoru Saeki,
Tetsuya Ichikawa:
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level.
IEICE Transactions 90-A(1): 160-168 (2007) |
| 4 | EE | Minoru Saeki,
Daisuke Suzuki,
Tetsuya Ichikawa:
Leakage Analysis of DPA Countermeasures at the Logic Level.
IEICE Transactions 90-A(1): 169-178 (2007) |
| 2005 |
|---|
| 3 | EE | Daisuke Suzuki,
Minoru Saeki,
Tetsuya Ichikawa:
DPA Leakage Models for CMOS Logic Circuits.
CHES 2005: 366-382 |
| 2000 |
|---|
| 2 | | Tetsuya Ichikawa,
Tomomi Kasuya,
Mitsuru Matsui:
Hardware Evaluation of the AES Finalists.
AES Candidate Conference 2000: 279-285 |
| 1 | EE | Kazumaro Aoki,
Tetsuya Ichikawa,
Masayuki Kanda,
Mitsuru Matsui,
Shiho Moriai,
Junko Nakajima,
Toshio Tokita:
Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms - Design and Analysis.
Selected Areas in Cryptography 2000: 39-56 |
