| |
| 2007 | ||
|---|---|---|
| 2 | EE | Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang: A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. ISCAS 2007: 3051-3054 |
| 1999 | ||
| 1 | EE | Woogeun Rhee: Design of low-jitter 1-GHz phase-locked loops for digital clock generation. ISCAS (2) 1999: 520-523 |
| 1 | Baoyong Chi | [2] |
| 2 | Zhihua Wang | [2] |
| 3 | Xueyi Yu | [2] |