| 2008 |
|---|
| 12 | | Mihai Nica,
Bernhard Peischl,
Franz Wotawa:
A Constraint Model for Automated Deployment of Automotive Control Software.
SEKE 2008: 899-904 |
| 11 | EE | Bernhard Peischl,
Naveed Riaz,
Franz Wotawa:
Advances in Automated Source-Level Debugging of Verilog Designs.
New Challenges in Applied Intelligence Technologies 2008: 363-372 |
| 2007 |
|---|
| 10 | EE | Bernhard K. Aichernig,
Martin Weiglhofer,
Bernhard Peischl,
Franz Wotawa:
Test purpose generation in an industrial application.
A-MOST 2007: 115-125 |
| 9 | | Bernhard Peischl,
Martin Weiglhofer,
Franz Wotawa:
Executing Abstract Test Cases.
GI Jahrestagung (2) 2007: 416-421 |
| 8 | EE | Bernhard K. Aichernig,
Bernhard Peischl,
Martin Weiglhofer,
Franz Wotawa:
Protocol Conformance Testing a SIP Registrar: an Industrial Application of Formal Methods.
SEFM 2007: 215-226 |
| 2006 |
|---|
| 7 | EE | Bernhard Peischl,
Safeeullah Soomro,
Franz Wotawa:
Towards Lightweight Fault Localization in Procedural Programs.
IEA/AIE 2006: 660-667 |
| 6 | EE | Bernhard Peischl,
Franz Wotawa:
Automated Source-Level Error Localization in Hardware Designs.
IEEE Design & Test of Computers 23(1): 8-19 (2006) |
| 2005 |
|---|
| 5 | EE | Bernhard Peischl,
Franz Wotawa:
Error traces in model-based debugging of hardware description languages.
AADEBUG 2005: 43-48 |
| 2004 |
|---|
| 4 | | Bernhard Peischl,
Franz Wotawa:
Are Error Traces Enough for Automated Fault Localization in VHDL Designs?
WISES 2004: 49-60 |
| 2003 |
|---|
| 3 | EE | Daniel Köb,
Bernhard Peischl,
Franz Wotawa:
Debugging VHDL Designs Using Temporal Process Instances.
IEA/AIE 2003: 402-415 |
| 2 | EE | Bernhard Peischl,
Franz Wotawa:
Modeling State in Software Debugging of VHDL-RTL Designs - A Model-Based Diagnosis Approach
CoRR cs.AI/0311001: (2003) |
| 1 | EE | Bernhard Peischl,
Franz Wotawa:
Model-Based Diagnosis or Reasoning from First Principles.
IEEE Intelligent Systems 18(3): 32-37 (2003) |
