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Vu-Duc Ngo

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2007
9EESeongmin Noh, Daehyun Kim, Vu-Duc Ngo, Hae-Wook Choi: Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip. ISPA 2007: 268-277
8EEHuy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi: An QoS Aware Mapping of Cores Onto NoC Architectures. ISPA 2007: 278-288
7EEVu-Duc Ngo, June-Young Chang, Younghwan Bae, Hanjin Cho, Hae-Wook Choi: Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling. ISPA 2007: 289-302
2006
6EEVu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi: The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. ISPA 2006: 75-85
5EEVu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi: Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. ISPA Workshops 2006: 791-802
2005
4 Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi: Realization of video object plane decoder on mesh on-chip network architecture. Circuits, Signals, and Systems 2005: 137-141
3EEVu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi: Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. EUC 2005: 300-310
2EEHuy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi: Realization of Video Object Plane Decoder on On-Chip Network Architecture. ICESS 2005: 256-264
1EEVu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi: Designing On-Chip Network Based on Optimal Latency Criteria. ICESS 2005: 287-298

Coauthor Index

1Younghwan Bae [5] [7] [8]
2June-Young Chang [7]
3Hanjin Cho [5] [7] [8]
4Hae-Wook Choi [1] [2] [3] [4] [5] [6] [7] [8] [9]
5Daehyun Kim [9]
6Huy Nam Nguyen [1] [2] [3] [4] [5] [6] [8]
7Seongmin Noh [9]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)