| 2007 |
|---|
| 12 | EE | Seongmin Noh,
Daehyun Kim,
Vu-Duc Ngo,
Hae-Wook Choi:
Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip.
ISPA 2007: 268-277 |
| 11 | EE | Huy Nam Nguyen,
Vu-Duc Ngo,
Younghwan Bae,
Hanjin Cho,
Hae-Wook Choi:
An QoS Aware Mapping of Cores Onto NoC Architectures.
ISPA 2007: 278-288 |
| 10 | EE | Vu-Duc Ngo,
June-Young Chang,
Younghwan Bae,
Hanjin Cho,
Hae-Wook Choi:
Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling.
ISPA 2007: 289-302 |
| 2006 |
|---|
| 9 | EE | Vu-Duc Ngo,
Huy Nam Nguyen,
Hae-Wook Choi:
The Optimum Network on Chip Architectures for Video Object Plane Decoder Design.
ISPA 2006: 75-85 |
| 8 | EE | Vu-Duc Ngo,
Huy Nam Nguyen,
Younghwan Bae,
Hanjin Cho,
Hae-Wook Choi:
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder.
ISPA Workshops 2006: 791-802 |
| 7 | EE | Sang-Ho Seo,
Hae-Wook Choi,
Sin-Chong Park:
Low Latency and Memory Efficient Viterbi Decoder Using Modified State-Mapping Method.
IEICE Transactions 89-B(4): 1413-1416 (2006) |
| 6 | EE | Ho-Seok Choi,
Hae-Wook Choi,
Sin-Chong Park:
Instruction Based Synthesizable Testbench Architecture.
IEICE Transactions 89-C(5): 653-657 (2006) |
| 5 | EE | Jungbo Son,
Hae-Wook Choi,
Sin-Chong Park:
Accelerating Verification with Reusable Testbench.
IEICE Transactions 89-D(2): 853-856 (2006) |
| 2005 |
|---|
| 4 | | Huy Nam Nguyen,
Vu-Duc Ngo,
Hae-Wook Choi:
Realization of video object plane decoder on mesh on-chip network architecture.
Circuits, Signals, and Systems 2005: 137-141 |
| 3 | EE | Vu-Duc Ngo,
Huy Nam Nguyen,
Hae-Wook Choi:
Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design.
EUC 2005: 300-310 |
| 2 | EE | Huy Nam Nguyen,
Vu-Duc Ngo,
Hae-Wook Choi:
Realization of Video Object Plane Decoder on On-Chip Network Architecture.
ICESS 2005: 256-264 |
| 1 | EE | Vu-Duc Ngo,
Huy Nam Nguyen,
Hae-Wook Choi:
Designing On-Chip Network Based on Optimal Latency Criteria.
ICESS 2005: 287-298 |
