| |
| 1993 | ||
|---|---|---|
| 2 | Suhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan: FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview. VLSI Design 1993: 73-79 | |
| 1 | EE | B. Naveen, K. S. Raghunathan: An Automatic Netlist-to-Schematic Generator. IEEE Design & Test of Computers 10(1): 36-41 (1993) |
| 1 | Suhail Ahmed | [2] |
| 2 | P. K. Fangaria | [2] |
| 3 | T. V. Nagesh | [2] |
| 4 | K. S. Raghunathan | [1] [2] |
| 5 | Ramoji Rao | [2] |